MANHASSET, NY — The latest research developments in interconnect technologies will be featured at IITC this summer. The two most interesting trends: 3D ICs and nanotube interconnects. The International Interconnect Technology Conference (Burlingame, Calif., June 2 - 4) is a forum to address interconnect issues from the system level.

"Interconnect" is the wiring system that connects transistors and other components on an integrated circuit. The interconnect problem threatens to retard the development of chip technology. Papers presented at IITC address this problem.

This year, Georgia Tech, IBM and Nanonexus researchers will describe an integrated microfluidic heat sink technology for 3D integrated circuits. The primary challenge with stacked chips is how to remove the heat generated by their operation. For example, the power density of two stacked high-performance microprocessors may be as much as 200W/cm2, implying a heat flux beyond the capacity of current fan-cooling technology.

The heat sinks developed by the researchers are on the backside of each chip. Coolant is delivered by means of fluidic through-silicon vias (TSVs) and pipes. Deionized water is pumped through the microchannels at a flow rate of 65ml/min. The microchannels and TSVs were formed in one etch step, a key advance over previous work. Afterward, a sacrificial polymer was used to fill and protect them while another layer was built. The polymer then was decomposed at high temperature to create the TSV/channel structure. It takes up minimal surface area.

Another paper reports on the progress of the first test of carbon nanotubes as interconnects in a circuit.

As copper wires scale to narrower dimensions, their resistivity will increase to the point that the chip's overall performance will suffer. Carbon nanotubes have a lower theoretical resistivity than does copper but, until now, they haven't been used as actual interconnects in a real CMOS integrated circuit.

At IITC, a Stanford University and Toshiba team will tell how it built a 0.25-m CMOS test chip containing an array of ring oscillators. Each ring oscillator was deliberately missing an interconnect wire, which was replaced with a multi-walled carbon nanotube (MWCNT) on top of the chip. The MWCNTs were 30-nm in diameter and up to 14-micron long.

The team measured sub-ns delays attributable to the nanotubes (a good figure of merit), but say the actual resistance of the MWCNTs is some 150 times greater than theory would predict, illustrating an important gap between the static resistance and the dynamic behavior of MWCNTs. Also, the team says its integration strategy isn't limited just to multi-walled nanotubes, and that single-walled nanotubes, bundles of MWCNTs and even nanowires could be integrated similarly.

Stanford University holds its own interconnects conference later this year.

The IITC brings together more than 700 professionals to discuss science and technology issues in the advanced interconnect technology field.