MANHASSET, NY — As a natural extension of trends in the test and measurement business, the electronics industry is moving toward embedded instrumentation. Leading this movement is Asset InterTech Inc., a company that began as a business unit of Texas Instruments dedicated to the development of IEEE 1149.1 tools.

Instrumentation is being embedded in chips, on circuit boards and in systems for design validation, test and debug. A new standard--IEEE P1687 Internal JTAG (IJTAG)--is currently being developed to control, manage, schedule, analyze and access the instrumentation that is being embedded at the core level of chips. The IJTAG standard will rely on the boundary-scan embedded infrastructure in chips and on boards.

Asset, through its ScanWorks platform, is developing open embedded instrumentation tools based on the preliminary P1687 IJTAG specifications.

"The trajectory of the industry has been moving toward non-intrusive methodologies for more than 15 years, ever since boundary-scan technology came on the scene," said CEO Glenn Woppman. "Embedding instrumentation is the next logical step."

The proliferation of embedded instrumentation in the industry has numerous players.

For instance, Intel's IBIST is being deployed throughout the company's high-end chips and chip sets. Some of Synopsys's DesignWare Verification Library modules can be integrated into Verilog, SystemVerilog, OpenVera and VHDL test benches to generate and respond to bus traffic, check for protocol violations and generate coverage reports that can be incorporated into chip designs. Vitesse Semiconductor has devised a two-channel approach to obtain an eye diagram or other instrumentation plots that validate the performance of high-speed receivers. And Logic Vision's embedded SerDes loop-back solution structurally characterizes the parameters that determine signal eye distortion tolerances, verifying the parameters designers consider during a SerDes core design.

Recently, Asset joined the Mentor Graphics OpenDoor Program to enable the exchange of data between Mentor's chip-level inserted design"for-test (DFT) structures, such as the JTAG infrastructure and Asset's ScanWorks platform.

Initial efforts will include interoperability testing for both the original boundary-scan standard, IEEE 1149.1, as well as for the newer IEEE 1149.6 standard, which specifies a test methodology for high-speed, differential interconnects.