Decoding Manchester-encoded data
Decoding Manchester-encoded data is as easy as encoding it. You simply perform an exclusive-OR of the Manchester-encoded signal with a logical "1" at the bit-boundary sample points, as shown in Figure 6.

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If you prefer an analog solution for decoding, Figure 7 shows a simple circuit that can achieve the same results. The beauty of this circuit, sometimes called a data-slicer, is that it doesn't require a synchronizing clock. This eliminates the possibly of errors caused by clock jitters or mismatches between the transmitting and receiving clock signals. The only issue is the values selected for the resistor and capacitor. They must be selected so that the RC-time constant is longer than 1/2 the bit-boundary period. This will prevent detection during a setup period. While Figure 7 represents a conceptual view, in practice you would want to create some positive feedback around the amplifier. The positive feedback will provide hysteresis that will help filter out noise that could possibly be misinterpreted as a real Manchester-encoded transition.

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Once the hysteresis and the RC-time constant have been properly setup, the circuit will reliably decode Manchester-encoded signals. You will also notice that this circuit will work for both Option A and Option B.

Clock synchronization
Another intrinsic value to Manchester encoding is the fact that the synchronizing clock is embedded within the signal. This fact is exploited in Ethernet, which uses on-board circuitry to maintain clock synchronization. A Digital Phase Locked Loop (DPLL) circuit monitors the incoming Manchester-encoded signal and makes adjustments to its internal oscillator to keep it in constant synchronization with the transmitter's clock frequency.

The DPLL functions by sampling the incoming Manchester-encoded data with its own local clock. A simple shift register, driven by the local clock, accumulates all the shifted bits.

If the local oscillator is in synchronization with the transmitter's clock, there will be an equal number of binary 1's and 0's across the shift register. If an imbalance occurs between binary 1's and 0's, the local clock is adjusted based on the number of binary bits off center. This is why you will find a preamble at the beginning of each packet transmitted via Ethernet.

Each Ethernet packet starts with an 8-byte (64 bit) preamble, which is used by the DPLL to "lock" into the correct frequency. Since the preamble doesn't contain useful data, no data is lost. However, it does add more overhead to the data stream.