Crosstalk occurs when capacitive coupling between two nets allows a switching transient on one net to inject charge onto the other due to voltage gradient on these nets. In the parlance of the field, these nets are referred to as the aggressor and victim.

The circuit elements defining this transfer of energy is given by the equation I = C * dV/dt. Some of the factors affecting crosstalk include:

1) Every net has a Ground Cap value of its own (Cg).

2) Cg defines the ability of a net to resist a change in its state.

3) Coupling Cap (Cc) defines the ability of a net to bring a change in state of the coupled net.

4) Crosstalk α Cc/Cg. Currently, crosstalk-aware routing implies routing the clock nets with double spacing. Also, the width is doubled. Owing to these constraints, more routing resources are used.

5) In design involving few metal layers, it becomes a tedious task to implement the clock and data routes with Doublespace, Double-width attribute.

6) With shrinking design nodes, it is becoming increasingly difficult to route the design that meets all the required crosstalk sensitive guidelines.

7) This constraint gives rise to congested designs more often than not.

8) To fix the congestion and achieve 100 percent clean routing with such strict guidelines shall consume valuable manhours.

9) To save on congestion, avoid over-designing we need to modify the crosstalk-aware routing guidelines.

10) More prudent crosstalk aware routing shall lead to better post-route optimized design which shall save our die-size.

Double width, double space
Our idea involves around identifying how to filter out the clock-nets, which must be routed with "double width and double space attribute." This would help us save on congestion and hence save valuable man-hours, better optimized design and in-turn saves the die-size.

Presently, most of the design teams across the globe route the clock-nets with double width and double space. This is done since:

1) Clock nets are more sensitive to noise because they toggle the most; and,

2) Increasing the spacing of the clock nets would decrease the effect of Cc since capacitance is inversely proportional to spacing.

The drawback with this strategy is that it overkills the design (especially for SoCs where routing resources are at a premium). Because of routing with double spacing and double width attribute, valuable routing resources are used. This, in turn, shall give a less optimized post-routed design and hence diesize would increase. Any increment in die-size means more cost.